Clock synchronization across 1Msps ADCs

Hi Dave,

Yes, I have the flexibility to calibrate across all channels simultaneously. I'm planning to design this feature into it for my own sanity! So, it would be a feasible option to correct for any delays after the board is fabricated. I would not want to introduce FIR filters in my FPGA for each channel unless absolutely necessary, though. Worst case scenario, the data could be collected with the FPGA and post-processed offline where computational load isn't a hard requirement. This would unfortunately preclude me from doing any processing on-board in realtime.

I'm looking at fairly high dynamic range (16-24 bits, differential inputs), but more important than dynamic range is phase matching across channels. I will need to look closely at my jitter requirements to make sure the PLL can meet this. Otherwise, DDS may be a better approach as you suggested.

I appreciate you sharing the CARMA board. It's a neat application. I'll have a closer look today at how you approached the problem. There's certainly some things I can learn from it!

-Jason