Forum Discussion
Honored Contributorclock Pin warning
Hello,
How do I get rid of this warning?warning: clocks_pll_1|nios_pll_1|altpll_component|auto_generated|pll1|clk[1] could not be matched with a port or pin or register or keeper or net.[/I][/I] Thanks, AA
14 Replies
Altera_ForumMost likely clk[2] and clk[4] were synthesized out. That's either because they don't drive logic(perhaps the logic they drive was synthesized out), or possibly it was merged with an identical output of the PLL.
- Altera_Forum
I can find "clocks_pll_1\|ncr_pll_1\|altpll_component\|auto_generated\|pll1\|clk\[1\]" in the Name Finder.
- Altera_Forum
Hello Rysc
I have a PLL. The input to the PLL is coming from a port on the FPGA. The PLL generates 5 clock frequencies [clk[0] to clk[4]]. In Time Quest when I go to "Create Generated Clock" I am not able to find the pins "clk[2] and clk[4]" [in the target filed]. Does this have anything to do with the location of the port [which is an input to PLL] on FPGA ?. [ie different pin locations have different properties associated with them] Thanks, AA - Altera_Forum
It's from your .sdc file. You might be able to double-click on the warning in TimeQuest and it will take you to the location, but it doesn't always work. If not, just search on that name in your .sdc file. I don't know what constraint it's in or what it's supposed to match, but something seems wrong. Use TimeQuest's View -> Name Finder to help. (There's a space in the word "generated", but it seems like that would cause another error...)
