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Honored Contributor
Honored Contributorclock Pin warning
Hello, How do I get rid of this warning? warning: clocks_pll_1|nios_pll_1|altpll_component|auto_generated|pll1|clk[1] could not be matched with a port or pin or register or keeper or ne...
Altera_ForumHonored Contributor
Honored ContributorHello Rysc
I have a PLL. The input to the PLL is coming from a port on the FPGA. The PLL generates 5 clock frequencies [clk[0] to clk[4]]. In Time Quest when I go to "Create Generated Clock" I am not able to find the pins "clk[2] and clk[4]" [in the target filed]. Does this have anything to do with the location of the port [which is an input to PLL] on FPGA ?. [ie different pin locations have different properties associated with them] Thanks, AA
