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Altera_Forum
Honored Contributor
Honored Contributorclock Pin warning
Hello, How do I get rid of this warning? warning: clocks_pll_1|nios_pll_1|altpll_component|auto_generated|pll1|clk[1] could not be matched with a port or pin or register or keeper or ne...
Altera_ForumHonored Contributor
Honored ContributorMost likely clk[2] and clk[4] were synthesized out. That's either because they don't drive logic(perhaps the logic they drive was synthesized out), or possibly it was merged with an identical output of the PLL.
