Hello, How do I get rid of this warning? warning: clocks_pll_1|nios_pll_1|altpll_component|auto_generated|pll1|clk[1] could not be matched with a port or pin or register or keeper or net.[/I][/I] Thanks, AA

It's from your .sdc file. You might be able to double-click on the warning in TimeQuest and it will take you to the location, but it doesn't always work. If not, just search on that name in your .sdc file. I don't know what constraint it's in or what it's supposed to match, but something seems wrong. Use TimeQuest's View -> Name Finder to help. (There's a space in the word "generated", but it seems like that would cause another error...)

Hello Rysc I have a PLL. The input to the PLL is coming from a port on the FPGA. The PLL generates 5 clock frequencies [clk[0] to clk[4]]. In Time Quest when I go to "Create Generated Clock" I am not able to find the pins "clk[2] and clk[4]" [in the target filed]. Does this have anything to do with the location of the port [which is an input to PLL] on FPGA ?. [ie different pin locations have different properties associated with them] Thanks, AA

Most likely clk[2] and clk[4] were synthesized out. That's either because they don't drive logic(perhaps the logic they drive was synthesized out), or possibly it was merged with an identical output of the PLL.

Okay thanks. a) How do I know when to use the option "Set False Path" b) In the Summary(setup) two clocks have negative slack, how do I fix it? Thanks, AA

clock Pin warning | Altera Community

14 Replies

Altera_Forum
Honored Contributor
14 years ago
alteraaditya - You sent me a private message, but your settings block private messages, so I couldn't reply. It sounds like you have a failing path that is correctly constrained but doesn't meet timing. If it's close, then maybe some Quartus II settings will help. Look at Tools -> Advisors -> Timing Optimization Advisor. The first few are the ones you want.
Another option is changing speed grades or family. Not ideal, but that's why they're there(unless you're using the fastest Stratix IV already). Finally, you may have to re-architect to shorten the datapath. That's often the best solution, but takes a lot of work. Good luck.
Altera_Forum
Honored Contributor
14 years ago
Hello Rysc,

Can you look into the post number 91 under the thread "Questions about Monitor". I don't want to re-post it here again.

Thanks,
Aditya
Altera_Forum
Honored Contributor
14 years ago
i got this warning too
Altera_Forum
Honored Contributor
14 years ago
hate this warning

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clock Pin warning

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