Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorclock Pin warning
Hello, How do I get rid of this warning? warning: clocks_pll_1|nios_pll_1|altpll_component|auto_generated|pll1|clk[1] could not be matched with a port or pin or register or keeper or ne...
Altera_ForumHonored Contributor
Honored Contributoralteraaditya - You sent me a private message, but your settings block private messages, so I couldn't reply. It sounds like you have a failing path that is correctly constrained but doesn't meet timing. If it's close, then maybe some Quartus II settings will help. Look at Tools -> Advisors -> Timing Optimization Advisor. The first few are the ones you want.
Another option is changing speed grades or family. Not ideal, but that's why they're there(unless you're using the fastest Stratix IV already). Finally, you may have to re-architect to shorten the datapath. That's often the best solution, but takes a lot of work. Good luck.
