Forum Discussion
Honored Contributorclock Pin warning
Hello,
How do I get rid of this warning?warning: clocks_pll_1|nios_pll_1|altpll_component|auto_generated|pll1|clk[1] could not be matched with a port or pin or register or keeper or net.[/I][/I] Thanks, AA
14 Replies
Altera_Forumhate this warning
- Altera_Forum
i got this warning too
- Altera_Forum
Hello Rysc,
Can you look into the post number 91 under the thread "Questions about Monitor". I don't want to re-post it here again. Thanks, Aditya - Altera_Forum
alteraaditya - You sent me a private message, but your settings block private messages, so I couldn't reply. It sounds like you have a failing path that is correctly constrained but doesn't meet timing. If it's close, then maybe some Quartus II settings will help. Look at Tools -> Advisors -> Timing Optimization Advisor. The first few are the ones you want.
Another option is changing speed grades or family. Not ideal, but that's why they're there(unless you're using the fastest Stratix IV already). Finally, you may have to re-architect to shorten the datapath. That's often the best solution, but takes a lot of work. Good luck. - Altera_Forum
I came across the document you have created about TQ Analyzer. Thanks! It definitely cleared some of my doubts
- Altera_Forum
Umm...no it wasn't a multicycle setup. Okay I will think about this. I have another question. It is already posted in "Question about Monitor" [the last message in this thread is my question about IO pins]. Can you take a look at it. I dont want to re-post it here.
- Altera_Forum
Most likely it is not.
1) Is this path really a multicycle setup, i.e. was it designed so that when the source register launches data, it won't be captured until two latch cycles later? If not, you've loosened the timing requirements so it passes timing but the hardware will fail. 2) If it is correct, did you add a multicycle hold to prevent the hold requirement from following the setup(explained in the User Guide I put together)? - Altera_Forum
Thanks. What I did was, I right clicked on the violated path and selected "Set Multi-cycle" [between clock nodes] and set the multicycle number to the most negative slack shown in the report. This got rid of the error [Changed from Red to Black] Is this the right way to do it ?
- Altera_Forum
a) Your design may have paths that TimeQuest is analyzing but that you have explicitly designed to behave asynchronously. An example might be an error signal coming out of one domain(and held high) and asynchronously sampled in another domain(and double-registered to remove metastability). Another example might be a signal that is static, i.e. it comes up as a 1 or a 0, but never changes after that.
Note that you write a design and need to know how it should be timed. The .sdc just tells TimeQuest how it should be designed. It doesn't work the other way though, i.e. if you add a set_false_path to something that doesn't make it so that the circuit behaves asynchronously. (It's a terrible mistake when a user adds a false path to something that really needs to be made synchronous. The system will break in hardware, the probelm is usually not simulatable, and it takes serious low-level debug to find the issue.) b) There are about 50 things to do, if not more. First off, right-click and do Report Timing. That will break out the failing paths in detail. Some things to look at: - Are the clocks synchronous to each other? (It may be a false path if they are not) - Is the setup relatiosnhip correct? - Is the clock skew small? (If it's not, you may have a clock skew problem rather than a long data path delay issue) Once those are checked, it now comes to analyzing the datapath, in that it is too long to meet timing. It's hard to comment without seeing more. - Altera_Forum
Okay thanks.
a) How do I know when to use the option "Set False Path" b) In the Summary(setup) two clocks have negative slack, how do I fix it? Thanks, AA
