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Altera_Forum
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15 years ago

clock Pin warning

Hello, How do I get rid of this warning? warning: clocks_pll_1|nios_pll_1|altpll_component|auto_generated|pll1|clk[1] could not be matched with a port or pin or register or keeper or ne...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Thanks. What I did was, I right clicked on the violated path and selected "Set Multi-cycle" [between clock nodes] and set the multicycle number to the most negative slack shown in the report. This got rid of the error [Changed from Red to Black] Is this the right way to do it ?