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Altera_Forum
Honored Contributor
Honored Contributorclock Pin warning
Hello, How do I get rid of this warning? warning: clocks_pll_1|nios_pll_1|altpll_component|auto_generated|pll1|clk[1] could not be matched with a port or pin or register or keeper or ne...
Altera_ForumHonored Contributor
Honored ContributorMost likely it is not.
1) Is this path really a multicycle setup, i.e. was it designed so that when the source register launches data, it won't be captured until two latch cycles later? If not, you've loosened the timing requirements so it passes timing but the hardware will fail. 2) If it is correct, did you add a multicycle hold to prevent the hold requirement from following the setup(explained in the User Guide I put together)?
