Honored ContributorHello there,
I have 2 external clocks and currently I have assigned them to - Pin 91 of bank 6 with 3.3 LVTTL - Pin 22 of bank 1 with 3.0 LVTTL of my EP3C5E144C8 FPGA However Quartus is giving a warning that these pins do no abide to altera's requirement for 3.3 V, 3.0V and 2.5V interfaces. Can anyone please give me some hints what to look for and how to fix this ? thanks John
Honored ContributorWhat's the error message? I/O banks are programmable, i.e. they can be configured to support different voltages, but all I/O in that bank must use the same voltage reference. Usually no-fits caused by this are because other pins in the same bank require a different voltage. The no-fit error usually expands to to show where the conflict is.
Another place to look is the Pin Planner. You can use it to list all I/O in that bank and look at their voltage. You can also run an I/O analyzer to do quick checks, rather than running a full compile and waiting for it to error out in the fitter.Honored ContributorApplication Note 447 (Interfacing Cyclone III Devices with 3.3/3.0/2.5-V LVTTL/LVCMOS I/O Systems)
Honored ContributorThe following is the warning I receive:
--- Quote Start --- Warning: Following 2 pins must meet Altera requirements for 3.3V, 3.0V, and 2.5V interfaces. Info: Pin Clk1 uses I/O standard 3.0-V LVTTL at 22 Info: Pin Clk2 uses I/O standard 3.3-V LVTTL at 91 --- Quote End --- the VCCIO on the bank 6 is 3.3V and Bank 1 is 3.0V. I can't understand why I get that warning when I believe I'm respecting AN447 guidelines.Honored ContributorIt's a warning, not an error. Quartus doesn't say that you don't follow the rules, it just reminds you that you should.
You get this warning each time you use those I/O voltages on a Cyclone IIIHonored ContributorWell, I understand that this is a warning and I don't think that I mentioned the word error somewhere. However is it safe to ignore it or do clocks have a different voltage setup compare to the rest of the pins ?
Honored ContributorIt's like a watch your step warning in a bus. Altera don't want to be held responsible for FPGA damaged by overshooting input voltages.
Honored ContributorIt is safe to ignore it, as long as you read the AN and designed your board in accordance.
