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Altera_Forum's avatar
Altera_Forum
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17 years ago

clock pin assignments and cyclone III

Hello there, I have 2 external clocks and currently I have assigned them to - Pin 91 of bank 6 with 3.3 LVTTL - Pin 22 of bank 1 with 3.0 LVTTL of my EP3C5E144C8 FPGA However Quartus...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

It's like a watch your step warning in a bus. Altera don't want to be held responsible for FPGA damaged by overshooting input voltages.