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Altera_Forum's avatar
Altera_Forum
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17 years ago

clock pin assignments and cyclone III

Hello there, I have 2 external clocks and currently I have assigned them to - Pin 91 of bank 6 with 3.3 LVTTL - Pin 22 of bank 1 with 3.0 LVTTL of my EP3C5E144C8 FPGA However Quartus...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

The following is the warning I receive:

--- Quote Start ---

Warning: Following 2 pins must meet Altera requirements for 3.3V, 3.0V, and 2.5V interfaces.

Info: Pin Clk1 uses I/O standard 3.0-V LVTTL at 22

Info: Pin Clk2 uses I/O standard 3.3-V LVTTL at 91

--- Quote End ---

the VCCIO on the bank 6 is 3.3V and Bank 1 is 3.0V.

I can't understand why I get that warning when I believe I'm respecting AN447 guidelines.