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kaz, that makes a lot of sense. funny you mention it, I have a reset signal that changes very rarely that is also causing some timing issues. A false path there should solve that issue - the reset signal is valid for multiple cycles of the slowest clock.
rbugalho, I have a number of clocks in the system and no matter what they are (even 1:1 plls), I don't trust their relationships and I either double flop or use dcfifo for CDC. Would I still be lying to TimeQuest if I put all those clocks in groups?
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Anything but reset... if your reset means that signal for register reset then you can't put false path since every path will need synchroniser and this defeats the purpose. It is practical for few registers,
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