Forum Discussion
Honored ContributorClock failed
I got these warnings in Quartus. Please help me fix. :)
Warning: The master clock for this clock assignment could not be derived. Clock: pll|sd1|pll7|clk was not created.
Warning: Specified master clock: clk not found on or feeding the specified source node: pll|sd1|pll7|inclk
Warning: The master clock for this clock assignment could not be derived. Clock: pll|sd1|pll7|clk was not created.
Warning: Specified master clock: clk not found on or feeding the specified source node: pll|sd1|pll7|inclk
12 Replies
Altera_ForumI'm sorry, but I don't see this critical warning when I synthesize this.
I attached the project with the report files (.rpt) when you look in the Static Timing Analyzer report (.sta.rpt) you will see that there is no such warning. Which version of Quartus are you using? The example you gave me was created for version 11.0. I use 11.1 with service pack 2.- Altera_Forum
The original project and the example QAR have the same warning: :)
Critical Warning (332148): Timing requirements not met - Altera_Forum
I tried to reproduce the warning message you see. But I didn't see these messages when I synthesize this example.
I using Quartus II 11.1 SP2 just to make sure that the software version is not causing this. I attached my example QAR file to this message. Try this to see if you still see the warning messages. - Altera_Forum
If you can send me the link of the example you used, I can check this out.
- Altera_Forum
I didn't work. I can post the project if you want. :D
- Altera_Forum
Ok, in this case you need to modify or create a SDC file.
Here is an example which creates timing constraints for the 25 MHz input clock "clk_pin":create_clock -name clk -period 25MHz # derive PLL output clocks & add clock uncertainty derive_pll_clocks -create_base_clocks derive_clock_uncertainty - Altera_Forum
I did not change the name of the input clock pin. The orginal project also failed compiling. :D
- Altera_Forum
If you have change the name of the input clock pin you have to modify the SDC file accordingly.
- Altera_Forum
This is the project made for EP3C25F324C8 from Altera website, and I change the device and pin assignment to EP4CGX15BF14C8. The input clock is already defined in the project. :)
- Altera_Forum
It's a timinig analysis warning. You didn't define the input clock.
