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Altera_Forum's avatar
Altera_Forum
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14 years ago

Clock failed

I got these warnings in Quartus. Please help me fix. :) Warning: The master clock for this clock assignment could not be derived. Clock: pll|sd1|pll7|clk was not created. Warning: Specifie...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

This is the project made for EP3C25F324C8 from Altera website, and I change the device and pin assignment to EP4CGX15BF14C8. The input clock is already defined in the project. :)