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Altera_Forum's avatar
Altera_Forum
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14 years ago

Clock failed

I got these warnings in Quartus. Please help me fix. :) Warning: The master clock for this clock assignment could not be derived. Clock: pll|sd1|pll7|clk was not created. Warning: Specifie...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Ok, in this case you need to modify or create a SDC file.

Here is an example which creates timing constraints for the 25 MHz input clock "clk_pin": 


create_clock -name clk -period 25MHz 
#  derive PLL output clocks & add clock uncertainty
derive_pll_clocks -create_base_clocks
derive_clock_uncertainty