Honored ContributorHi
I'm running into fitting problems on a Stratix III with specified CLKCTRL blocks. The resource BLOCK_INPUT_MUX_X0_Y52_N0_I18 is used by more than one signal. I could not find documentation about an input mux for the clock control blocks. As it looks for me right now, they seem to exist and to be shared among the drivers ;) Does anyone have more information about how they are connected? Thanks emanuel
Honored ContributorHi Emanuel,
maybe it is a stupid question, but why are you place the mux by yourself ? Kind regards GerdHonored ContributorHi Gerd,
well, I'm not placing the MUX myself, but the driver. That's because the design is not really nice for an FPGA (it's made for an ASIC) and I'm trying to get a better timing (hold time violations). When I do this, I create situations, where I get fitter errors stating that these MUXes are used more than once. That's the only information I have about them... /EmanuelHonored ContributorHi Emanuel,
do you know the root cause of your Hold time violations ? Kind regards GerdHonored ContributorHi Gerd,
yes I do... But at the moment, there is no way to fix them. The FPGA is only a prototyping platform for an ASIC design, so that the software guys can develop their stuff. On the chip, it works "better" than on the FPGA, where the clock structure is totally incompatible to the design. Anyway, seems there is no real solution and as a) next Quartus version is supposed to be better on this issue and b) the design has to be "fixed" in any case, I should probably not waste to much energy on this issue ;) Thanks, emanuelHonored ContributorHi Emanuel,
we also use the FPGA's for ASIC prototyping. Of coarse we also run into problem, when we try to prototype the ASIC clock generation (Gated clocks etc.....). Sometimes we could simplify the clock generation , because the SW guy's did not need the real clock implementation. Sometimes we used Third Party Synthesis tools like SynplifyPro, because this tools could convert clock gating structures into clock enables. Kind regards GerhardHonored ContributorHi Gerhard,
that's a bit the question: How far are differences between the ASIC and the FPGA HDL acceptable. So far, the idea is to keep them as small as possible. The idea to use third party synthesis tools has probably not been discussed here so far, that would be an idea. On the other hand, Altera promised Quartus 8.1 in November and it is supposed to be able to do this conversion... Lets see what happens ;) Thanks and best regards, emanuel
