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Altera_Forum
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18 years ago

clkctrl input mux

Hi I'm running into fitting problems on a Stratix III with specified CLKCTRL blocks. The resource BLOCK_INPUT_MUX_X0_Y52_N0_I18 is used by more than one signal. I could not find documentat...
Altera_Forum's avatar
Altera_Forum
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18 years ago

Hi Gerhard,

that's a bit the question: How far are differences between the ASIC and the FPGA HDL acceptable. So far, the idea is to keep them as small as possible.

The idea to use third party synthesis tools has probably not been discussed here so far, that would be an idea. On the other hand, Altera promised Quartus 8.1 in November and it is supposed to be able to do this conversion... Lets see what happens ;)

Thanks and best regards,

emanuel