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Honored Contributor
Honored Contributorclkctrl input mux
Hi I'm running into fitting problems on a Stratix III with specified CLKCTRL blocks. The resource BLOCK_INPUT_MUX_X0_Y52_N0_I18 is used by more than one signal. I could not find documentat...
Altera_ForumHonored Contributor
Honored ContributorHi Emanuel,
we also use the FPGA's for ASIC prototyping. Of coarse we also run into problem, when we try to prototype the ASIC clock generation (Gated clocks etc.....). Sometimes we could simplify the clock generation , because the SW guy's did not need the real clock implementation. Sometimes we used Third Party Synthesis tools like SynplifyPro, because this tools could convert clock gating structures into clock enables. Kind regards Gerhard
