Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

clkctrl input mux

Hi I'm running into fitting problems on a Stratix III with specified CLKCTRL blocks. The resource BLOCK_INPUT_MUX_X0_Y52_N0_I18 is used by more than one signal. I could not find documentat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi Gerd,

yes I do... But at the moment, there is no way to fix them. The FPGA is only a prototyping platform for an ASIC design, so that the software guys can develop their stuff. On the chip, it works "better" than on the FPGA, where the clock structure is totally incompatible to the design.

Anyway, seems there is no real solution and as a) next Quartus version is supposed to be better on this issue and b) the design has to be "fixed" in any case, I should probably not waste to much energy on this issue ;)

Thanks,

emanuel