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Honored Contributor
Honored Contributorclkctrl input mux
Hi I'm running into fitting problems on a Stratix III with specified CLKCTRL blocks. The resource BLOCK_INPUT_MUX_X0_Y52_N0_I18 is used by more than one signal. I could not find documentat...
Altera_ForumHonored Contributor
Honored ContributorHi Gerd,
well, I'm not placing the MUX myself, but the driver. That's because the design is not really nice for an FPGA (it's made for an ASIC) and I'm trying to get a better timing (hold time violations). When I do this, I create situations, where I get fitter errors stating that these MUXes are used more than once. That's the only information I have about them... /Emanuel
