Capturing values during simulation with ModelSim

Hi,

I'm really in a hurry right now so I will bring just a very short reply. I will come with more details later.

I guess you are looking for something you can use in perl/tcl scripting, right?

For this you may want to use

exa -$radix sim:/full_hierarchical_path/signal_name

If it is not tcl nor perl but just logging of some data you may use assertions. PSL/verilog/systemverilog are handy and you may need just a short time to be able to create some loggers.

That's all for now.

Thanks dipling!

I think in my case loggers are okay, because I just need the data so another program can handle that.

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Thanks dipling!

I think in my case loggers are okay, because I just need the data so another program can handle that.

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You still did not tell me what you want/can use? Verilog, SystemVerilog, PSL?

How are you coding your design?

VHDL? In this case PSL should be used.

Verilog or SystemVerilog? Use builtin fwrite functions.

I may help you with an example if I know what you need.

Hi dipling,

I have an analizing program written in Java, that analyzes a NoC structure also written in Java.

I also have a NoC structure written in VHDL, that I would like to analyze too. My ideia is to simulate the VHDL code with ModelSim and capture all important signal values, so the Java program can handle that.

tks for the help!

Hi dipling,

I was thinking... and I guess tcl would be very suitable for my project. But I don't really know much about it.

Could you help me with a script that captures the value of a signal in each cycle of the clock and writes it into a output file?

Thanks a lot!