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Altera_Forum's avatar
Altera_Forum
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16 years ago

Capturing values during simulation with ModelSim

Hello, I am using ModelSim to simulate a VHDL code. Is there any way to capture values of certain signals during this simulation? I was thinking about a get command in the command line, or...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

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Thanks dipling!

I think in my case loggers are okay, because I just need the data so another program can handle that.

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You still did not tell me what you want/can use? Verilog, SystemVerilog, PSL?

How are you coding your design?

VHDL? In this case PSL should be used.

Verilog or SystemVerilog? Use builtin fwrite functions.

I may help you with an example if I know what you need.