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Altera_Forum's avatar
Altera_Forum
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16 years ago

Capturing values during simulation with ModelSim

Hello, I am using ModelSim to simulate a VHDL code. Is there any way to capture values of certain signals during this simulation? I was thinking about a get command in the command line, or...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi,

I'm really in a hurry right now so I will bring just a very short reply. I will come with more details later.

I guess you are looking for something you can use in perl/tcl scripting, right?

For this you may want to use

exa -$radix sim:/full_hierarchical_path/signal_name

If it is not tcl nor perl but just logging of some data you may use assertions. PSL/verilog/systemverilog are handy and you may need just a short time to be able to create some loggers.

That's all for now.