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Altera_Forum's avatar
Altera_Forum
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15 years ago

Can't understand the Tsu and Th defination in Quartus

Tsu=data delay-clock delay+uTsu;

Th=clock delay-data delay +uTh;

Take the defination of Tsu for example, we can get that longer the data delay, longer the Tsu, which is not understandable. The other one has similar question.

Despite this ,there is another question: what does the quartus do when we do not assign any value to timing parameter like tsu, th,tco. Does it use default values or it just use the worse case to do, for using utSU,utH....

Thanks

John

http://picasaweb.google.com/117586898586715593879/qs#5499675005290014882

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Are you using Classic TAN or TimeQuest?

    The micro parameters are fixed values. Just consider them delays for all intents and purposes. I didn't follow everything, but you state that the longer the data delay the longer the Tsu, which is not understandable. That is correct. Let's pretend the data delay is 6ns and the clock delay is 1ns(ignore everything else for now). In order for your data to get to the register before the clock, you need to have it at the device input 5ns before the clock is at the device input. If you don't, you will violate this Tsu requirement of 5ns. So the larger the data delay, the larger the Tsu requirement. Does that make sense?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks for reply.

    I am using Classic Time Analysis.

    I still can't get that.

    For simple, pretend clock delay is 0, then Tsu=data delay? What does data delay mean here?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Data delay is how long it takes a signal to get from the input port of the device to the register. If it's an I/O cell, it may be a short delay, but some designs might have combinatorial logic on the path, a huge data delay, and hence the Tsu of that data pin is really large. Let's say it's a 20ns Tsu. That means the device driving the FPGA needs to get it's data at the input at least 20ns before the next clock edge. If your clock period is 50ns, then the previous device basically has 30ns to work with, which is probably fine. But if your period is 25ns, that's probably too tight and it won't work.

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Hi John,

    The equations you given has nothing to do with the designer's perspective. It is purely about internal fpga timing of registers. You only need to enter fmax.

    It is up to the tool to get get them right. very few people take risk at floor planning to play with delays.

    However, at fpga input registers(under the mercy of incoming signal from external device) and at the registers of an external device under the mercy of fpga signal, it is your task to get tSU & tH timing right.

    The same above equations apply but with the delay being board delay plus what fpga puts between pins and registers.
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Appreciate for telling me the knowledge.

    I will consider it carefully.

    Here is another question. When I set the IO voltage to 3.3VTTL, and assign one pin to high, only to see that it is about 1.14V, but when I changed its place to another dual-in pin, it come back to 3.3V.

    P.S. the previous dula-in pins are used mostly.