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Altera_Forum
Honored Contributor
Honored ContributorCan't understand the Tsu and Th defination in Quartus
Tsu=data delay-clock delay+uTsu; Th=clock delay-data delay +uTh; Take the defination of Tsu for example, we can get that longer the data delay, longer the Tsu, which is not understandable. The o...
Altera_ForumHonored Contributor
Honored ContributorHi John,
The equations you given has nothing to do with the designer's perspective. It is purely about internal fpga timing of registers. You only need to enter fmax. It is up to the tool to get get them right. very few people take risk at floor planning to play with delays. However, at fpga input registers(under the mercy of incoming signal from external device) and at the registers of an external device under the mercy of fpga signal, it is your task to get tSU & tH timing right. The same above equations apply but with the delay being board delay plus what fpga puts between pins and registers.
