Can't understand the Tsu and Th defination in Quartus

Data delay is how long it takes a signal to get from the input port of the device to the register. If it's an I/O cell, it may be a short delay, but some designs might have combinatorial logic on the path, a huge data delay, and hence the Tsu of that data pin is really large. Let's say it's a 20ns Tsu. That means the device driving the FPGA needs to get it's data at the input at least 20ns before the next clock edge. If your clock period is 50ns, then the previous device basically has 30ns to work with, which is probably fine. But if your period is 25ns, that's probably too tight and it won't work.