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Roberto07's avatar
Roberto07
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3 years ago

Can't simulate ADC as shown in the tutorial

Hello,

I use Quartus Prime Lite Edition with Questa Intel FPGA Starter edition ver. 21.1 on a Win 11 PC, and I have a DE10-Lite board.

I followed an old, short tutorial to simulate the Altera Modular ADC IP:

https://www.youtube.com/watch?v=6UscboZ1Vho

I compiled the IP (.qip file), included the .sip file, attached the testbench and run the simulation.

Questa simulation starts, but stops during the optimization:


# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm -L fiftyfivenm_ver -L rtl_work -L work -L altera_trace_adc_monitor_wa_inst -L timing_adapter_1 -L timing_adapter_0 -L data_format_adapter_0 -L rst_controller -L trace_endpoint -L core -L avalon_st_adapter_001 -L avalon_st_adapter -L st_splitter_internal -L adc_monitor_internal -L control_internal -L modular_adc_0 -voptargs=""+acc"" tb_adctest
# Start time: 17:49:18 on Aug 12,2022
# ** Note: (vsim-3812) Design is being optimized...
# ** Error: E:/.../adcsimwoutf/simulation/submodules/adcsimwoutf_modular_adc_0_adc_monitor_internal.v(101): Module 'adcsimwoutf_modular_adc_0_adc_monitor_internal_core' is not defined.
# For instance 'core' at path 'tb_adctest.u0.modular_adc_0.adc_monitor_internal'
# ** Error: E:/.../adcsimwoutf/simulation/submodules/adcsimwoutf_modular_adc_0_adc_monitor_internal.v(121): Module 'adcsimwoutf_modular_adc_0_adc_monitor_internal_trace_endpoint' is not defined.
# For instance 'trace_endpoint' at path 'tb_adctest.u0.modular_adc_0.adc_monitor_internal'
# Optimization failed

Can you post a new tutorial to perform ADC simulation with output file similar to the 2018 one, but more detailed and working for newer Quartus and IP versions (in particular showing the compilation of all required blocks and a more detailed testbench, the one shown in the tutorial is completely missing pll clock)?

Thanks in advance,

Roberto.

20 Replies

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  • Roberto07's avatar
    Roberto07
    Icon for New Contributor rankNew Contributor
    3 years ago

    Hi Fakhrul,

    thank you for your support.

    However, the tutorial you suggested (https://www.intel.com/content/www/us/en/design-example/714441/max-10-adc-example-for-use-with-board-test-system-monitor-panel.html) is not what I am looking for.

    I do not want to test the ADC with the monitor panel.

    I want to see in Questa the waveforms shown at minute 3:06 of the video tutorial:

    https://www.youtube.com/watch?v=6UscboZ1Vho

    So I am only interested in the ADC core simulation with Questa.

    I attached a project where I tried to replicate the ADC waveforms in Questa, but both the vhdl and verilog ADC model doesn't work.

    This is the project I attached:

    https://community.intel.com/cipcp26785/attachments/cipcp26785/programmable-devices/86573/1/vhdlsimnotok.zip

    I have issues with the vhdl or verilog model of the ADC core, I don't know why it doesn't work in simulation.

    If you can help to make the hdl ADC core simulation model work thank you very much.

    Kind regards, Roberto.

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Roberto,


    I'll send a MAX 10 ADC simulation example file in a private message so you could try to run it on your end and let's see the outcome.


    Regards,

    Fakhrul




  • Roberto07's avatar
    Roberto07
    Icon for New Contributor rankNew Contributor
    3 years ago

    Yes, thank you very much.

    You can use the email vers.robe@ittmarconiforli.edu.it to send me the link to the simulation example file.

    I'm just interested in the ADC Core simulation, without sequencer with Avalon MM-storage.

    Regards,

    Roberto.

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Roberto,


    I wish to follow up with you about this forum case. So do you still have any further questions on this?

    Sorry I may have overlooked your reply. Anyway, I have already sent the example file through the private message, I hope you able to get the file.


    Regards,

    Fakhrul


  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Roberto,

    I've tried to send it to your email, but somehow it's been blocked and undeliverable.

    Anyway, here's the example of the ADC simulation, please try to run the project on your end. There are also simulated user-defined signal text files included. Please take note to use Verilog as we faced some problems running it with VHDL.

    Regards,

    Fakhrul

  • Roberto07's avatar
    Roberto07
    Icon for New Contributor rankNew Contributor
    3 years ago

    Thank you very much, I'll let you know asap.

    Regards,

    Roberto.

  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Roberto,


    I wish to follow up with you about this case. Do you have any updates?

    Otherwise, this thread will be idling and marked as inactive, thus it will be transitioned to community support because there is no update received from you in a while.


    Regards,

    Fakhrul



  • FakhrulA_altera's avatar
    FakhrulA_altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    Hi Roberto,


    As we do not receive any response from you to the previous reply.

    This thread will be transitioned to community support.

    If you have a new question, feel free to open a new thread to get support from Intel experts.

    Otherwise, the community users will continue to help you on this thread.


    Thank you