Forum Discussion
FakhrulA_altera
Regular Contributor
3 years agoHi Roberto,
I've tried to send it to your email, but somehow it's been blocked and undeliverable.
Anyway, here's the example of the ADC simulation, please try to run the project on your end. There are also simulated user-defined signal text files included. Please take note to use Verilog as we faced some problems running it with VHDL.
Regards,
Fakhrul