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Moti's avatar
Moti
Icon for New Contributor rankNew Contributor
4 years ago

can't define differential clock at MAX10

Hi

Facing Issue with Max10 CPLD, I can't define differential clock at my design.

I/O bank 6 is 1.8V, and I Used all Vref pins in the CPLD as single-ended I/O.

I tried to define the clock input as LVDS / Sub-LVDS , error :

Error (169029): Pin DIFF100_XTAL_OSC1_40MHZ is incompatible with I/O bank 6. Pin uses I/O standard Sub-LVDS, which has a VCCIO requirement incompatible with that bank's VCCIO setting or its other pins that use VCCIO 1.8V.

Error (169032): I/O bank 6 contains input or bidirectional pins with I/O standards that make it impossible to choose a legal VCCIO value for the bank

I would appreciate help regarding the define differential clock in the bank of 1.8V ?

I have also Stratix10 FPGA and I succeeded to define LVDS inputs at 1.8V bank

Thanks,

Moti

4 Replies

  • AminT_Intel's avatar
    AminT_Intel
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hello Moti,

    May I know which version of Quartus are you using?

    Try this workaround to solve Error 169029:

    1. Remove the location assignment of pin_perst
    2. Add a quartus.ini file in your project directory with: dft_skip_oct_vccn_check = on

    Try this workaround to solve Error 169032

    1. Assign 1.5V PCML I/O standard to Cyclone IV GX transceiver input pins.

    Thank you.