New Contributor
New ContributorThanks AminT for the fast response.
the version is Quartus standard 19.1,
I added the quartus.ini file and define the clock pin as Sub-LVDS, the 2 error are gone ( 169029 & 169032 ).
what causes the error in Quartus ?
but still the question is technical, can I now connect to the Max10 differential clock (of 1.8V at bank of 1.8V
and there is no any Vref from the pins to the CPLD) and define it as LVDS ? Sub-LVDS ?
Do they require Vref ? and what with others differential I/O 's ?
Thank you
Regular ContributorHello Moti,
The error is a known issue. You will need to refer to these two documents for your design I/O standard specification: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-gpio.pdf and https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10_datasheet.pdf .
Thank you.
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