When instantiating simplex Rx and Tx JESD cores generated by quartus, and enabling the reconfiguration interfaces, the following placement error shows: Error (12829): Failed to merge HSSI Avalon Memory-Mapped interface instances "main|devices[0].jesd204_rx_core|main|intel_arria_10.unit|intel_jesd204_core|jesd204_core|jesd204_0|inst_phy|inst_xcvr|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst" and "main|devices[0].jesd204_tx_core|main|intel_arria_10.unit|intel_jesd204_core|jesd204_core|jesd204_0|inst_phy|inst_xcvr|g_xcvr_native_insts[1].twentynm_xcvr_native_inst|twentynm_xcvr_native_inst|inst_twentynm_xcvr_avmm|avmm_atom_insts[0].twentynm_hssi_avmm_if_inst" into single Avalon Memory-Mapped Interface. The error is also described here, albeit for a different IP, but still the error is the same.. https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/ip/2020/error-12829---failed-to-merge-hssi-avalon-memory-mapped-interfac.html Another similar issue is here, which does seem to have a workaround https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd09282014_173.html So is there a workaround for my case as well, or is upgrading to latest quartus really necessary, and how do I know that this will in fact solve the issue without having to upgrade the entire design?

Hi,As I understand it, you encounter some issues when trying to place two simplex JESD instances into the same XCVR channel. To ensure we are on the same page, just would like to check with you on the following:1. What is the device that you are using?2. What is the Quartus version that you are using?3. Are you using JESD204B or JESD204C IP?4. Would you mind to share with me a simple test design with only the JESD instances which could replicate the error to facilitate further debugging.Please let me know if there is any concern. Thank you.Best regards,Chee Pin

Hi Hi that is correct. Please see answers below 1. What is the device that you are using? Arria 10 2. What is the Quartus version that you are using? 17.1 Pro 3. Are you using JESD204B or JESD204C IP? JESD204B 4. Would you mind to share with me a simple test design with only the JESD instances which could replicate the error to facilitate further debugging. Design is integrated in our top level can't share this, but attached a JESD Rx simplex and JESD Tx simplex example designs with their reconfiguration interfaces enabled and which also exhibit this issue. If you try to place JESD Tx and JESD Rx in same bank and transceiver channel, the error shows up.

Hi,Sorry for the delay. Thanks for sharing the designs. Please allow me some more time to debug into this. Please ping me if you do not hear from me by end of the week.

Hi, For your information, I have created a simple test design with simplex JESD204b TX and RX PHY only with dynamic reconfiguration enabled. I was able to merge both into the same XCVR channel. Attached is the QAR for your reference. Note that I am using PHY only to ease the demo. For your information, you should take note that you cannot merge if you have the following enabled: 1. ADME 2. Shared reconfig interface 3. Capability registers I believe you cannot enable the Control and status registers and PRBS soft accumulators as well but I could not be sure on these two. You may further test out if you need these. Please let me know if there is any concern. Thank you.

Hi,Just to follow up with you on this. Please let me know if there is any concern. Thank you.

Cannot merge HSSI Avalon Memory-Mapped interface instances for simplex JESD designs

26 Replies

CheepinC_altera
Regular Contributor
5 years ago
Hi,

As I understand it, you encounter some issues when trying to place two simplex JESD instances into the same XCVR channel. To ensure we are on the same page, just would like to check with you on the following:

1. What is the device that you are using?

2. What is the Quartus version that you are using?

3. Are you using JESD204B or JESD204C IP?

4. Would you mind to share with me a simple test design with only the JESD instances which could replicate the error to facilitate further debugging.

Please let me know if there is any concern. Thank you.

Best regards,
Chee Pin
- cheyert
  New Contributor
  5 years ago
  Hi
  
  Hi that is correct.
  
  Please see answers below
  
  1. What is the device that you are using?
  
  Arria 10
  
  2. What is the Quartus version that you are using?
  
  17.1 Pro
  
  3. Are you using JESD204B or JESD204C IP?
  
  JESD204B
  
  4. Would you mind to share with me a simple test design with only the JESD instances which could replicate the error to facilitate further debugging.
  
  Design is integrated in our top level can't share this, but attached a JESD Rx simplex and JESD Tx simplex example designs with their reconfiguration interfaces enabled and which also exhibit this issue. If you try to place JESD Tx and JESD Rx in same bank and transceiver channel, the error shows up.
  jesd_rx.tar.gz26 MB
  jesd_tx.tar.gz29.7 MB
CheepinC_altera
Regular Contributor
5 years ago
Hi,

Sorry for the delay. Thanks for sharing the designs. Please allow me some more time to debug into this. Please ping me if you do not hear from me by end of the week.
- CheepinC_altera
  Regular Contributor
  5 years ago
  Hi,
  
  For your information, I have created a simple test design with simplex JESD204b TX and RX PHY only with dynamic reconfiguration enabled. I was able to merge both into the same XCVR channel. Attached is the QAR for your reference. Note that I am using PHY only to ease the demo.
  
  For your information, you should take note that you cannot merge if you have the following enabled:
  
  1. ADME
  
  2. Shared reconfig interface
  
  3. Capability registers
  
  I believe you cannot enable the Control and status registers and PRBS soft accumulators as well but I could not be sure on these two. You may further test out if you need these.
  
  Please let me know if there is any concern. Thank you.
  a10_jesd_merge_170std.qar2.9 MB
  - cheyert
    New Contributor
    5 years ago
    Hello,
    
    Thanks for your message, but still no success.
    
    I did find this explanation on the error message here as well
    
    https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/hsio/2020/error-12829---failed-to-merge-hssi-avalon-memory-mapped-interfac.html
    
    which is quite similar.
    
    My flow uses tcl scripts, and when I write out the .tcl file for IP generation during the build phase, the only options I see are the following:
    
    set_instance_parameter_value jesd204_0 {TEST_COMPONENTS_EN} {0}
    set_instance_parameter_value jesd204_0 {bitrev_en} {0}
    set_instance_parameter_value jesd204_0 {bonded_mode} {non_bonded}
    set_instance_parameter_value jesd204_0 {gui_analog_voltage} {1_0V}
    set_instance_parameter_value jesd204_0 {gui_user_crete_tile} {etile}
    set_instance_parameter_value jesd204_0 {lane_rate} {9830.4}
    set_instance_parameter_value jesd204_0 {pll_reconfig_enable} {0}
    set_instance_parameter_value jesd204_0 {pll_type} {CMU}
    set_instance_parameter_value jesd204_0 {rcfg_enable_split_interface} {0}
    set_instance_parameter_value jesd204_0 {rcfg_jtag_enable} {0}
    set_instance_parameter_value jesd204_0 {rcfg_shared} {0}
    set_instance_parameter_value jesd204_0 {sdc_constraint} {1.0}
    set_instance_parameter_value jesd204_0 {set_capability_reg_enable} {0}
    set_instance_parameter_value jesd204_0 {set_csr_soft_logic_enable} {0}
    set_instance_parameter_value jesd204_0 {set_prbs_soft_logic_enable} {0}
    set_instance_parameter_value jesd204_0 {set_user_identifier} {0}
    set_instance_parameter_value jesd204_0 {wrapper_opt} {base_phy}
    set_instance_property jesd204_0 AUTO_EXPORT true
    
    and they are all disabled...But it still shows the error message.
    
    I also saw that your design only has 1 JESD lane, my design has 2 lanes...could that be interfering as well?
    jesd_tx.7z2 KB
CheepinC_altera
Regular Contributor
5 years ago
Hi,

Just to follow up with you on this. Please let me know if there is any concern. Thank you.
CheepinC_altera
Regular Contributor
5 years ago
Hi,

Can you try using the IP Editor flow to see if there is any difference?

Also, just would like to check with you if you are using E-Tile device? I saw the following:

set_instance_parameter_value jesd204_0 {gui_user_crete_tile} {etile}
- cheyert
  New Contributor
  5 years ago
  This .tcl file is generated from within the IP generator by writing it out from there...
  
  This ticket also mentions to disable those things.
  
  Workaround/Fix
  
  To avoid this error, option "NPDME", "optional reconfiguration logic" or "embedded reconfiguration streamer" need to be disabled in the Native PHY IP.
  
  But how can you disable this on JESD IP generation, as it creates wrappers for core + transceiver PHY?
  
  The device we use is the 10AS057H3F34E2SG
  - CheepinC_altera
    Regular Contributor
    5 years ago
    Hi,
    
    Regarding your latest inquiries on the dynamic reconfiguration options in the JESD204B IP, you can control these option at the IP Editor. Note that you might observer "Share reconfiguration interface" is ON and greyed out. As a workaround, you can set ON dynamic reconfiguration, set the number of lane = 2, then turn OFF the "Share reconfiguration interface". Then set the number of lane = 1. Please let me know if there is any concern. Thank you.
CheepinC_altera
Regular Contributor
5 years ago
Hi,

Thanks for your update. Please allow me some time to further look into this. Just to check with you if your design changing to 1 lane, can the merging successful? Just to help narrowing down if it is related to the number of lanes configured in the IP.

Thank you.
CheepinC_altera
Regular Contributor
5 years ago
Hi,

Just would like to follow up with you on this. Thank you.
CheepinC_altera
Regular Contributor
5 years ago
Hi,

As I understand it, it has been some time since I last heard from you. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
- cheyert
  New Contributor
  5 years ago
  Hello,
  
  I would like to keep this open because as to date I have no resolution to this issue yet.
  
  I'm pretty sure I've exhausted all options as mentioned in the discussion, so not sure how to proceed from here on this issue.
  - CheepinC_altera
    Regular Contributor
    5 years ago
    Hi,
    
    Just to check with you if you have had a chance to try with my previous 2 lanes design which mimic your configuration?
    
    Please let me know if there is any concern. Thank you.
    
    Best regards,
    Chee Pin

Forum Discussion

Cannot merge HSSI Avalon Memory-Mapped interface instances for simplex JESD designs

26 Replies

Workaround/Fix

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