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Honored Contributor
Honored ContributorCan lowering frequency cause design to not run
Hi
I have a question on running designs at lower frequencies. With my limited study in B.E about setup and hold time issues, I have learnt that lowering frequency can allow a design to run because it caters to setup time violation. But can there be a reason that design doesnt work on lowering the frequency? Thanks Anant3 Replies
Altera_ForumHold requirements are usually 0ns, meaning the same edge that launches data is the one that would latch a violation. Since only one edge of a clock is used for analysis(and failure), it doesn't matter what the frequency is. So if a design has a hold failure(and the requirement is 0, which it is for 99% of the paths in a design), then it will still fail at lower frequencies, even if you lowered it down to the hertz range.
- Altera_Forum
If you reduce the clock far enough things like DRAM won't work - they need refresh cycles at a specific rate.
Similarly some devices (some microprocessors, but probably not FPGAs) use capacitors as internal memory cells - so have a minimum operating frequency. - Altera_Forum
PLLs & transceivers also have minimum operating frequencies.
