JET60200
Contributor
ContributorCan A10 PCIE BAR{2] access memory size be increased to 1GB （to access FPGA DDR4 1GB memory)
hello,
we are testing A10 PCIE FPGA example & PCIE Linux driver ( follow link : https://fpgacloud.intel.com/devstore/platform/18.0.0/Pro/arria-10-pcie-gen3-x8-dma/). After building FPGA example and run test on Linux PC, we found dmesg shows:
"
[ 129.056373] Altera DMA: altera_dma_init(), Nov 6 2020 02:45:14
[ 129.056391] Altera DMA 0000:01:00.0: enabling device (0000 -> 0002)
[ 129.056436] Altera DMA 0000:01:00.0: pci_enable_device() successful
[ 129.056455] Altera DMA 0000:01:00.0: irq 39 for MSI/MSI-X
[ 129.056461] Altera DMA 0000:01:00.0: pci_enable_msi() successful
[ 129.056463] Altera DMA 0000:01:00.0: using a 64-bit irq mask
[ 129.056464] Altera DMA 0000:01:00.0: irq pin: 1
[ 129.056465] Altera DMA 0000:01:00.0: irq line: 11
[ 129.056465] Altera DMA 0000:01:00.0: irq: 39
[ 129.056466] Altera DMA 0000:01:00.0: request irq: 11
[ 129.056467] Altera DMA 0000:01:00.0: BAR[0] 0xc0000000-0xc00001ff flags 0x0014220c, length 512
[ 129.056468] Altera DMA 0000:01:00.0: BAR[1] 0x00000000-0x00000000 flags 0x00000000, length 0
[ 129.056469] Altera DMA 0000:01:00.0: BAR[2] 0xa0000000-0xbfffffff flags 0x0014220c, length 536870912
[ 129.056470] Altera DMA 0000:01:00.0: BAR[3] 0x00000000-0x00000000 flags 0x00000000, length 0
[ 129.056470] Altera DMA 0000:01:00.0: BAR[4] 0x00000000-0x00000000 flags 0x00000000, length 0
[ 129.056471] Altera DMA 0000:01:00.0: BAR[5] 0x00000000-0x00000000 flags 0x00000000, length 0
[ 129.056480] Altera DMA 0000:01:00.0: BAR[0] mapped to 0xffffc900031e6000, length 512
[ 129.056978] Altera DMA 0000:01:00.0: BAR[2] mapped to 0xffffc90040000000, length 536870912
"
as you can see, PCIE message shows " BAR[2] 0xa0000000-0xbfffffff , length 536870912
which means BAR[2] access address space is totally “= 0x20000000 bytes = 536870912 bytes "(512MBytes)
But our FPGA has 1GB DDR4 ,and we want PCIE BAR[2] can read/write the whole 1GB FPGA DDR4 from Host PCIE interface, so how can we do to implement this ? Where to config PCIE BAR[2] to access "1gb" address space in paltform designer ?
Thanks a lot
