Honored ContributorHi,
I am facing an issue while using byte enable memory. My memory is
Honored ContributorI want to add that this behavior varies with build to build i.e. some time RAM works correct. Some time I get a corrupted data at the output and some times no output. Different synthesis results in different outcomes
Honored ContributorWhat FPGA target are you using? Did you get any critical warning from TimeQuest? I don't really understand what you did on the read port. Are you using a 400MHz clock or 200MHz?
Honored ContributorThanks for the reply Daixiwen, I am using EP4SGX230KF40C2 FPGA and the read clock running at 400MHz. Instead of using an alternating signal made using 400MHz, I used 200MHz clock and connected it with the read port. There is no related warning in the TimeQuest report
Honored ContributorI'm still not sure I'm getting it. Do you want to read only every other cycle? In that case why don't you use a 200MHz clock and keep the read signal always at 1?
Are the other signals connected to the read port in the 400MHz clock domain?Honored ContributorNo, I want to read at every cycle of 400Mhz but since the depth of RAM is 2 so the possible values of addresses are 0 and 1 thats why i simply connected the 200MHz clock with read port of the RAM. In other words I read address 0 of RAM at a clock cycle of 400MHz and address 1 at the following clock cycle of 400MHz clock.
Just to remove your curiousity, there is a lot of RAMs (total 138), each RAM occupies 4M9ks. This setup was made to save a big lot of registers (total 52,992 Registers). So Its hard to avoid this setup and I need to make these RAMs work. As I mentioned earlier there is an uncertainty about the working condition of these RAMs. We have 4 similar boards and we are getting different behaviors of RAMs at different boards with same bit file. We are not able to identify any fault in hardware setup because if board0 works with bit file0 the same board fails to work with a different bit file. Thanks for showing your interest....Honored ContributorOh I see.. by read port you meant the address port. Now I get it.
I'd suggest to use a real signal that you toggle at each clock cycle instead of the 200MHz clock though, I don't know if Timequest would pick up the setup and hold requirements correctly when using a clock as an input signal. It's better to have all the signals (inputs and outputs) on the read port synchronized with the read clock. What options did you select for the memory blocks? According to the datasheet if the read-during-write behaviour is set to "old value" then the memory block is limited to 375MHz. It should be fine with the other settings though. Are your clock constraints set correctly? Does Timequest see all your internal clocks, with the correct frequencies?Honored ContributorOk it my trying synch read address instead of clock. I checked mega-wizard but i didn't find 'read during write operation limitation'. I am using a dual clock byte enable based memory and in this case this option didn't appear. Also I am doing read operation during write because read address is connected to the clock. I thought this should not effect the write section I mean i wont mind if the output of the memory is unstable for a few cycles (while writing).
Clocks are correctly constrained and Timequest is indicating proper clocks' frequenciesHonored ContributorIIRC the memory block latches the read address on every clock [1], so the output bits change some time before the following clock.
So you need to generate a 'read address' signal that changes every time the 400MHz clock changes - eg from a simple divide by 2 block. Make sure all the logic uses the same odd/even signal! A 200Mhz clock signal (generated by a PLL) probably won't have the guaranteed relationship to the 400Mhz clock. [1] assuming the clock-enable / address-hold (why are these named with opposite polarity?) doesn't affect things.
