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Altera_Forum
Honored Contributor
Honored ContributorByte Enabled RAM Issue
Hi, I am facing an issue while using byte enable memory. My memory is 128-bit wide dual clocked read clock runs at 400MHz while write clock runs at 200MHz Its depth is only 2 ...
Altera_ForumHonored Contributor
Honored ContributorIIRC the memory block latches the read address on every clock [1], so the output bits change some time before the following clock.
So you need to generate a 'read address' signal that changes every time the 400MHz clock changes - eg from a simple divide by 2 block. Make sure all the logic uses the same odd/even signal! A 200Mhz clock signal (generated by a PLL) probably won't have the guaranteed relationship to the 400Mhz clock. [1] assuming the clock-enable / address-hold (why are these named with opposite polarity?) doesn't affect things.
