Honored Contributor
Honored ContributorIIRC the memory block latches the read address on every clock [1], so the output bits change some time before the following clock.
So you need to generate a 'read address' signal that changes every time the 400MHz clock changes - eg from a simple divide by 2 block. Make sure all the logic uses the same odd/even signal! A 200Mhz clock signal (generated by a PLL) probably won't have the guaranteed relationship to the 400Mhz clock. [1] assuming the clock-enable / address-hold (why are these named with opposite polarity?) doesn't affect things.
