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Altera_Forum's avatar
Altera_Forum
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12 years ago

Bus LVDS in Cynclone V

Hi,

I tried to implement Bus LVDS in Cyclone V. But I Couldn't Analysis & Synthesis with errors as follows.

21207 "OEOUT" port of the single-ended output buffer "pdo:inst2|pdo_wys" is not connected

21207 "OEBOUT" port of the single-ended output buffer "pdo:inst2|pdo_wys" is not connected

I have already read the AN 522 document, but the problem is not solved.

I used both Quartus II version 13.1. and 13.0 SP1.

When I tried to do it in other device, Cyclone iii and Arria ii, Analysis & Synthesis was succeeded.

Do I need an extra step in Cyclone V ?

Thank you for help.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Bus LVDS is not supported in Cyclone V.

    This is a IO limitation, not a tool limitation. (It sucks I know) To do this with Cyclone V you need to use two physical pins, and LVDS_TX with OE, and LVDS_RX pins physically externally connected together.

    If you check the Cyclone V handbook, you will see it doesn't mention BUS LVDS

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Quick note: I just double checked the handbook. Looks like it may be a bit more complicated than that. In you may need to use the "Emulated LVDS mode" since it states the true LVDS mode doesn't support tristate.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Thanks for your reply.

    I see Cyclone V doesn't support Bus LVDS and tristate.

    Therefore I will use 2.5-V Differential SSTL instead of BLVDS I/O standard.

    The following document states Bus LVDS can be implemented in Cynclone V using with 2.5-V Differential SSTL.

    Is it not right?

    http://www.altera.com/literature/an/an522.pdf