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Altera_Forum
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12 years ago

Bus LVDS in Cynclone V

Hi, I tried to implement Bus LVDS in Cyclone V. But I Couldn't Analysis & Synthesis with errors as follows. 21207 "OEOUT" port of the single-ended output buffer "pdo:inst2|pdo_wys" is not...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Thanks for your reply.

I see Cyclone V doesn't support Bus LVDS and tristate.

Therefore I will use 2.5-V Differential SSTL instead of BLVDS I/O standard.

The following document states Bus LVDS can be implemented in Cynclone V using with 2.5-V Differential SSTL.

Is it not right?

http://www.altera.com/literature/an/an522.pdf