Broken JTAG-chain Cyclon V SoC
Hello
Issue: In our design with a Cyclone V SoC 5CSXFC6D6F31I7N we have the JTAG-chain: HPS->FPGA. With the Quartus Prime Programmer Standard Edition und USB-Blaster (terasIC) we see a JTAG-response from the FPGA (see attached screen shot), however, none from the HPS. We find this behavior on both prototype boards, and therefore do not assume a random soldering issue.
Analysis: Using an oscilloscope, we find that HPS_TDI, HPS_TCK, HPS_TMS and TCK, TMS, TDO seem fine, i.e. at least change states. Unfortunately, we do not have access to HPS_TDO and TDI as they are routed directly. The MSEL[0..4] are set to GND and we verified the power supplies on the different banks. See our schema in attachment.
Questions: is the JTAG-chain HPS->FPGA the correct choice? And if yes, are there any special requirements or settings to consider for this configuration? Is there another test we could do to localize the issue?
Many thanks for any hints.
Cheers
Mathias