Broken JTAG-chain Cyclon V SoC

I think you have your connections backwards. You have JTAG_TDI going to HPS_TDI. I think you should have JTAG_TDO going to HPS_TDI and JTAG_TDI going to the FPGA's TDO, unless this is just a naming issue in your design (which looking at it again I think it is).

I'm going by the DE1-SoC schematics from Terasic (download the "CD-ROM"): https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=836&PartNo=4#contents

Also note that MSEL all low means you're doing an HPS boot-first setup, meaning the HPS is responsible for programming the FPGA after it boots. I don't know if that's a part of this issue, but FYI.