Honored ContributorDoes anyone here know how to implement BRAM in Altera Quartus?? The inferred BRAM in my design isn't working in my synthesizer and i get logic instead of BRAM. Thats why compilation of my design failed
Regards, Bruno Kasimin
Honored ContributorNow i have data stored in .mif file as memory content of altsyncram0 block. In my files in working directory, there is alsyncram0.vhd which is automatically generated by the creation of block. Is it fixed or i can edit it? i need to put in behaviour of the block. you can see my attachment of helloworld.vhd which contains RAM data and its behaviour.
Honored ContributorYou may edit the vhd file if you know exactly which parameters of the Altsyncram block are affected by your changes. You can use this vhd file as any other VHDL source file in your top level design.
But you can also recall the Megawizard to make changes on the block or you can edit the mif file if you just need to change the content of the ROM.Honored ContributorThis is the generated VHDL file of the asyncram block:
ENTITY altsyncram0 IS PORT ( address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0); address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0); clock : IN STD_LOGIC ; data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0); wren_a : IN STD_LOGIC := '1'; wren_b : IN STD_LOGIC := '1'; q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0) ); END altsyncram0; ARCHITECTURE SYN OF altsyncram0 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0); COMPONENT altsyncram GENERIC ( address_aclr_a : STRING; address_aclr_b : STRING; address_reg_b : STRING; indata_aclr_a : STRING; indata_aclr_b : STRING; indata_reg_b : STRING; init_file : STRING; intended_device_family : STRING; lpm_type : STRING; numwords_a : NATURAL; numwords_b : NATURAL; operation_mode : STRING; outdata_aclr_a : STRING; outdata_aclr_b : STRING; outdata_reg_a : STRING; outdata_reg_b : STRING; power_up_uninitialized : STRING; read_during_write_mode_mixed_ports : STRING; widthad_a : NATURAL; widthad_b : NATURAL; width_a : NATURAL; width_b : NATURAL; width_byteena_a : NATURAL; width_byteena_b : NATURAL; wrcontrol_aclr_a : STRING; wrcontrol_aclr_b : STRING; wrcontrol_wraddress_reg_b : STRING ); PORT ( wren_a : IN STD_LOGIC ; clock0 : IN STD_LOGIC ; wren_b : IN STD_LOGIC ; address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0); address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0); q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0); data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0) ); END COMPONENT; BEGIN q_a <= sub_wire0(31 DOWNTO 0); q_b <= sub_wire1(31 DOWNTO 0); altsyncram_component : altsyncram GENERIC MAP ( address_aclr_a => "NONE", address_aclr_b => "NONE", address_reg_b => "CLOCK0", indata_aclr_a => "NONE", indata_aclr_b => "NONE", indata_reg_b => "CLOCK0", init_file => "F:/hello.mif", intended_device_family => "Cyclone", lpm_type => "altsyncram", numwords_a => 4096, numwords_b => 4096, operation_mode => "BIDIR_DUAL_PORT", outdata_aclr_a => "NONE", outdata_aclr_b => "NONE", outdata_reg_a => "CLOCK0", outdata_reg_b => "CLOCK0", power_up_uninitialized => "FALSE", read_during_write_mode_mixed_ports => "DONT_CARE", widthad_a => 12, widthad_b => 12, width_a => 32, width_b => 32, width_byteena_a => 1, width_byteena_b => 1, wrcontrol_aclr_a => "NONE", wrcontrol_aclr_b => "NONE", wrcontrol_wraddress_reg_b => "CLOCK0" ) PORT MAP ( wren_a => wren_a, clock0 => clock, wren_b => wren_b, address_a => address_a, address_b => address_b, data_a => data_a, data_b => data_b, q_a => sub_wire0, q_b => sub_wire1 ); END SYN; First of all, i have created the behaviour of the block: process (clk) begin if (clk'event and clk = '1') then if (wren_a = '1') and (wren_b = '1') and (address_a=address) and (data_a/=data_b) then report "write collision" severity failure; end if; if (wren_a = '1') then ram(to_integer(unsigned(address_a))) := data_a; q_a <= data_a; else q_a <= ram(to_integer(unsigned(address_a))); end if; if (wren_a = '1') then ram(to_integer(unsigned(address_b))) := data_b; q_b <= data_b; else q_b <= ram(to_integer(unsigned(address_b))); end if; end if; end process; Now i'm having difficulty on where i should put this code in generated vhdl from asyncram. anyone has idea?Honored ContributorI suggest you to create a top-level bdf file in which you create a schematic with connections between block symbols.
Every vhdl file that you have created can be transformed into a block symbol by opening the vhdl file and using the menu File --> Create/Update --> Create symbol files for current file In the top level bdf file you can insert each block symbol that you have created in this way. The connections between the blocks can be created using wires and busses. In this way you can connect your altsyncram block to the surrounding blocks by simple wires, without having to modify its automatically generated code. I hope this helps.Honored Contributori understand what you meant but the outputs of the asyncram block are actually are also output in my created vhdl files. So what i think is, my vhdl should be internal,i mean created vhdl must be somewhere inside the the altsyncram block and is not external as you mentioned before.I'm still confused about this.Further hints???
Honored ContributorThe altsyncram block is the source of your data (since you have used it in ROM mode) and can be instantiated directly by placing the block symbol into the top-level schematic. The block symbol will automatically recall the vhdl file which has been generated by Quartus II. So, if you use the schematic approach, you don't have to care about the vhdl file because it will be already "embedded" into the block symbol.
Honored ContributorI've tought about something. Is there any process already made in asyncram block i created?
Honored ContributorThe altsyncram block by itself does not include any process. The process that you have created (that you have called "the behaviour") is to be implemented as a stand-alone controller block outside the altsyncram block.
So the altsyncram is a simple data container and your external controller block decides when and how to read data from the memory. I hope that it is clear enough.Honored ContributorIs it possible to locate BRAMs in the Chip Planner?
