BRAM implementation in Altera Quartus

This is the generated VHDL file of the asyncram block:

ENTITY altsyncram0 IS

PORT

(

address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0);

address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);

clock : IN STD_LOGIC ;

data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

wren_a : IN STD_LOGIC := '1';

wren_b : IN STD_LOGIC := '1';

q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)

);

END altsyncram0;

ARCHITECTURE SYN OF altsyncram0 IS

SIGNAL sub_wire0 : STD_LOGIC_VECTOR (31 DOWNTO 0);

SIGNAL sub_wire1 : STD_LOGIC_VECTOR (31 DOWNTO 0);

COMPONENT altsyncram

GENERIC (

address_aclr_a : STRING;

address_aclr_b : STRING;

address_reg_b : STRING;

indata_aclr_a : STRING;

indata_aclr_b : STRING;

indata_reg_b : STRING;

init_file : STRING;

intended_device_family : STRING;

lpm_type : STRING;

numwords_a : NATURAL;

numwords_b : NATURAL;

operation_mode : STRING;

outdata_aclr_a : STRING;

outdata_aclr_b : STRING;

outdata_reg_a : STRING;

outdata_reg_b : STRING;

power_up_uninitialized : STRING;

read_during_write_mode_mixed_ports : STRING;

widthad_a : NATURAL;

widthad_b : NATURAL;

width_a : NATURAL;

width_b : NATURAL;

width_byteena_a : NATURAL;

width_byteena_b : NATURAL;

wrcontrol_aclr_a : STRING;

wrcontrol_aclr_b : STRING;

wrcontrol_wraddress_reg_b : STRING

);

PORT (

wren_a : IN STD_LOGIC ;

clock0 : IN STD_LOGIC ;

wren_b : IN STD_LOGIC ;

address_a : IN STD_LOGIC_VECTOR (11 DOWNTO 0);

address_b : IN STD_LOGIC_VECTOR (11 DOWNTO 0);

q_a : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

q_b : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);

data_a : IN STD_LOGIC_VECTOR (31 DOWNTO 0);

data_b : IN STD_LOGIC_VECTOR (31 DOWNTO 0)

);

END COMPONENT;

BEGIN

q_a <= sub_wire0(31 DOWNTO 0);

q_b <= sub_wire1(31 DOWNTO 0);

altsyncram_component : altsyncram

GENERIC MAP (

address_aclr_a => "NONE",

address_aclr_b => "NONE",

address_reg_b => "CLOCK0",

indata_aclr_a => "NONE",

indata_aclr_b => "NONE",

indata_reg_b => "CLOCK0",

init_file => "F:/hello.mif",

intended_device_family => "Cyclone",

lpm_type => "altsyncram",

numwords_a => 4096,

numwords_b => 4096,

operation_mode => "BIDIR_DUAL_PORT",

outdata_aclr_a => "NONE",

outdata_aclr_b => "NONE",

outdata_reg_a => "CLOCK0",

outdata_reg_b => "CLOCK0",

power_up_uninitialized => "FALSE",

read_during_write_mode_mixed_ports => "DONT_CARE",

widthad_a => 12,

widthad_b => 12,

width_a => 32,

width_b => 32,

width_byteena_a => 1,

width_byteena_b => 1,

wrcontrol_aclr_a => "NONE",

wrcontrol_aclr_b => "NONE",

wrcontrol_wraddress_reg_b => "CLOCK0"

)

PORT MAP (

wren_a => wren_a,

clock0 => clock,

wren_b => wren_b,

address_a => address_a,

address_b => address_b,

data_a => data_a,

data_b => data_b,

q_a => sub_wire0,

q_b => sub_wire1

);

END SYN;

First of all, i have created the behaviour of the block:

process (clk)

begin

if (clk'event and clk = '1') then

if (wren_a = '1') and (wren_b = '1') and (address_a=address) and (data_a/=data_b) then

report "write collision" severity failure;

end if;

if (wren_a = '1') then

ram(to_integer(unsigned(address_a))) := data_a;

q_a <= data_a;

else

q_a <= ram(to_integer(unsigned(address_a)));

end if;

if (wren_a = '1') then

ram(to_integer(unsigned(address_b))) := data_b;

q_b <= data_b;

else

q_b <= ram(to_integer(unsigned(address_b)));

end if;

end if;

end process;

Now i'm having difficulty on where i should put this code in generated vhdl from asyncram. anyone has idea?