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Altera_Forum
Honored Contributor
Honored ContributorBRAM implementation in Altera Quartus
Does anyone here know how to implement BRAM in Altera Quartus?? The inferred BRAM in my design isn't working in my synthesizer and i get logic instead of BRAM. Thats why compilation of my design fail...
Altera_ForumHonored Contributor
Honored Contributori understand what you meant but the outputs of the asyncram block are actually are also output in my created vhdl files. So what i think is, my vhdl should be internal,i mean created vhdl must be somewhere inside the the altsyncram block and is not external as you mentioned before.I'm still confused about this.Further hints???
