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Altera_Forum's avatar
Altera_Forum
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17 years ago

bit by bit Data transfer

Hello All..

I have problem in my code. I have created code for transmitting the data bit by bit.

i.e.if my input (FCH)=1010101010101010=AAh

then I'm Expecting 1010101010101010=AAh at tx_line one bit for one clock pulse.

but below code gives only first bit at output side.

Please correct my code :-reply to bcpatil3@yahoo.co.in

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Tx is

port(tx_line :out std_logic;

addr_1 :in std_logic_vector(47 downto 0);

fcs :in std_logic_vector(31 downto 0);

fsc :in std_logic_vector(15 downto 0);

buff_ptr :in std_logic_vector(23 downto 0);

fch :in std_logic_vector(15 downto 0);

did :in std_logic_vector(15 downto 0);

clk,rst_n :in std_logic);

end Tx;

architecture Behavioral of TFB is

begin

process(clk)

variable mux_sel:std_logic_vector(2 downto 0):="000";

begin

if (clk' event and clk='1') then

if (rst_n='0')then

tx_line<='0';

end if;

case mux_sel is

when "000" =>for i in 0 to 15 loop

tx_line<=fch(i);

end loop;

mux_sel:=mux_sel+1;

when "001" =>for i in 0 to 15 loop

tx_line<=did(i);

end loop;

mux_sel:=mux_sel+1;

when "010" =>for i in 0 to 47 loop

tx_line<=addr_1(i);

end loop;

mux_sel:=mux_sel+1;

when "011" =>for i in 0 to 15 loop

tx_line<=fsc(i);

end loop;

mux_sel:=mux_sel+1;

when "100" =>for i in 0 to 15 loop

tx_line<=buff_ptr(i);

end loop;

mux_sel:=mux_sel+1;

when "101" =>for i in 0 to 31 loop

tx_line<=fcs(i);

end loop;

mux_sel:=mux_sel+1;

when others =>tx_line<='0';

end case;

end if;

end process;

end Behavioral;

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    The statements inside the clock'event block are executed in parallel within a single clock cycle, also an iteration loop. In your example, only the last bit ist actually send. You can increment e. g. a bit counter to transmit one bit per clock cycle or use a shift register that is initially loaded with the parallel data and shifted out one bit each cycle.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi

    I'm new to this subject, Thank u for ur valuable sugestion.By using parallel in serial out shift register,we can resolve this problem. but i dont want to use shift register,so can u modify above code to get desired result without shift register.please....

    Thanx

    bc_2008
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    When doing parallel to serial conversions, I thing a shift register is really the most efficient way. Please tell me why you don't want to use it.

    Stefaan
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi

    There is no any particular region.just i want to transmit input data on

    single bit transmit line. That is fch(16 bit),did(16 bit,address(48 bit) and etc... on single transmit line one after another i.e fch then did and address one by one continuously.please please edit the above code to get the correct result,we can use any thing there is no restriction for this problem.please edit above code ...waiting for ur reply.very urgent.....

    Regards and thanx

    bc_2008
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Mr BC

    I still can not see why you should not use a shift register, and how you will use this in any practical design? If you tell me, maybe I can understand... As far as I can read VHDL, you just try to make a multiplexer driven by a counter.

    How are you going to synchronise the data again on the other end? Do you really want to run this serial line on the clock speed of the system? Is your clock is very slow?

    If you say you can resolve with a shift register, do it with a shift register then. It will be faster, less logic, simple implementation, ...

    Maybe you should latch your parallel data all at the same time before you send it out. Otherwise if some inputs change during the sending, the receiver sees inconsistent data.

    Stefaan
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Without considering the question, if it's a meaningful application, I corrected your code by keeping the original structure as far as possible: 

    process(clk)
  variable mux_sel:std_logic_vector(2 downto 0):="000";
  variable i: integer range 0 to 63;
begin
  if (clk' event and clk='1') then
    if (rst_n='0')then
      tx_line<='0';
      mux_sel:="000";
      i:=0;
    end if;
  case mux_sel is
    when "000" =>
      tx_line<=fch(i);
      i:=i+1;
      if i > fch'high then
        mux_sel:=mux_sel+1;
        i:=0;
      end if;
-- continue respectively
  end case;

    See the full design as attachment.

    I understand, that a frame sync character is used, so the data could be possibly received without additional synchronisation. Regarding Stefaan's question, if the baud rate is actually intended to be full clock speed, I think it basically could be. I have a sensor interface using a 40 MHz UART frame from a MAX II device, but it uses a 320 MHz clock at the receiving FPGA. (160 MHz would be a minimum).

    As Stefaan mentioned, the input has to be stable during transmission for consistent data. I also expect a lower resource requirement using a shift register, but in any case a lot of LEs is needed as multiplexer. If the timing constraints can be met with the existing construct, it must not necessarily changed.

    Frank

    P.S.: In case of a synchronous transmission, the frame could be received with the same clock.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    hi

    Thanx a lot, i follow ur sugestions.once again Thank you..........

    rgards and thanks

    bc patil
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    --- Quote Start ---

    Mr BC

    I still can not see why you should not use a shift register, and how you will use this in any practical design? If you tell me, maybe I can understand... As far as I can read VHDL, you just try to make a multiplexer driven by a counter.

    How are you going to synchronise the data again on the other end? Do you really want to run this serial line on the clock speed of the system? Is your clock is very slow?

    If you say you can resolve with a shift register, do it with a shift register then. It will be faster, less logic, simple implementation, ...

    Maybe you should latch your parallel data all at the same time before you send it out. Otherwise if some inputs change during the sending, the receiver sees inconsistent data.

    Stefaan

    --- Quote End ---

    Hi

    there is no point to use 1 bit counter.Can u guide me how to use shift register for solving this problem,possible edit above code and forward so i can analyze...please

    thankx

    bc
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Hi

    I need another one help,please help me.Here i wrote vhdl code for 32 bit crc for 2 bits of input data. please can anybody ulter this code

    for 32 bits of input data.If u have any other vhdl or verilog code (CRC-32 and 32 bit data) please forward to me.

    please...

    Vhdl code:

    library IEEE;

    use IEEE.STD_LOGIC_1164.ALL;

    use IEEE.STD_LOGIC_ARITH.ALL;

    use IEEE.STD_LOGIC_UNSIGNED.ALL;

    entity CRC_BLOCK is

    port (

    fcs:out std_logic_vector(31 downto 0);

    CLK:in std_logic;

    data:in std_logic_vector(1 downto 0);

    Reset_n:in std_logic);

    end CRC_BLOCK;

    architecture Behavioral of CRC_BLOCK is

    begin

    process(CLK)

    variable Dividend: std_logic_vector(34 downto 0);--make it 34 and check

    variable quo1:std_logic_vector(31 downto 0);

    variable rem1: std_logic_vector(33 downto 0);

    variable g:integer;

    variable polynomial:std_logic_vector(32 downto 0);--G(X)

    constant n:std_logic_vector(32 downto 0):="100000000000000000000000000000000";

    begin

    if(CLK'event and CLK = '1')then

    if(Reset_n = '0')then

    quo1 := (others=>'0');

    polynomial:="100000100110000010001110110110111";

    dividend := data * n;--M(X)*X32

    rem1(33 downto 0):=dividend(33 downto 0);

    fcs(31 downto 0) <= rem1(31 downto 0);

    else

    if (g=1) then

    quo1:= (others=>'0');

    else

    if(rem1 >= polynomial )then

    rem1 (0) := rem1(1) xor polynomial(0);

    rem1 (1) := rem1(2) xor polynomial(1);

    rem1 (2) := rem1(3) xor polynomial(2);

    rem1 (3) := rem1(4) xor polynomial(3);

    rem1 (4) := rem1(5) xor polynomial(4);

    rem1 (5) := rem1(6) xor polynomial(5);

    rem1 (6) := rem1(7) xor polynomial(6);

    rem1 (7) := rem1(8) xor polynomial(7);

    rem1 (8) := rem1(9) xor polynomial(8);

    rem1 (9) := rem1(10) xor polynomial(9);

    rem1 (10) := rem1(11) xor polynomial(10);

    rem1 (11) := rem1(12) xor polynomial(11);

    rem1 (12) := rem1(13) xor polynomial(12);

    rem1 (13) := rem1(14) xor polynomial(13);

    rem1 (14) := rem1(15) xor polynomial(14);

    rem1 (15) := rem1(16) xor polynomial(15);

    rem1 (16) := rem1(17) xor polynomial(16);

    rem1 (17) := rem1(18) xor polynomial(17);

    rem1 (18) := rem1(19) xor polynomial(18);

    rem1 (19) := rem1(20) xor polynomial(19);

    rem1 (20) := rem1(21) xor polynomial(20);

    rem1 (21) := rem1(22) xor polynomial(21);

    rem1 (22) := rem1(23) xor polynomial(22);

    rem1 (23) := rem1(24) xor polynomial(23);

    rem1 (24) := rem1(25) xor polynomial(24);

    rem1 (25) := rem1(26) xor polynomial(25);

    rem1 (26) := rem1(27) xor polynomial(26);

    rem1 (27) := rem1(28) xor polynomial(27);

    rem1 (28) := rem1(29) xor polynomial(28);

    rem1 (29) := rem1(30) xor polynomial(29);

    rem1 (30) := rem1(31) xor polynomial(30);

    rem1 (31) := rem1(32) xor polynomial(31);

    rem1 (32) := rem1(33) xor polynomial(32);

    quo1 := quo1 + 1;

    end if;

    if(rem1 >= polynomial )then

    rem1(32 downto 0) := rem1(31 downto 0) & '0';

    rem1 (0) := rem1(0) xor polynomial(0);

    rem1 (1) := rem1(1) xor polynomial(1);

    rem1 (2) := rem1(2) xor polynomial(2);

    rem1 (3) := rem1(3) xor polynomial(3);

    rem1 (4) := rem1(4) xor polynomial(4);

    rem1 (5) := rem1(5) xor polynomial(5);

    rem1 (6) := rem1(6) xor polynomial(6);

    rem1 (7) := rem1(7) xor polynomial(7);

    rem1 (8) := rem1(8) xor polynomial(8);

    rem1 (9) := rem1(9) xor polynomial(9);

    rem1 (10) := rem1(10) xor polynomial(10);

    rem1 (11) := rem1(11) xor polynomial(11);

    rem1 (12) := rem1(12) xor polynomial(12);

    rem1 (13) := rem1(13) xor polynomial(13);

    rem1 (14) := rem1(14) xor polynomial(14);

    rem1 (15) := rem1(15) xor polynomial(15);

    rem1 (16) := rem1(16) xor polynomial(16);

    rem1 (17) := rem1(17) xor polynomial(17);

    rem1 (18) := rem1(18) xor polynomial(18);

    rem1 (19) := rem1(19) xor polynomial(19);

    rem1 (20) := rem1(20) xor polynomial(20);

    rem1 (21) := rem1(21) xor polynomial(21);

    rem1 (22) := rem1(22) xor polynomial(22);

    rem1 (23) := rem1(23) xor polynomial(23);

    rem1 (24) := rem1(24) xor polynomial(24);

    rem1 (25) := rem1(25) xor polynomial(25);

    rem1 (26) := rem1(26) xor polynomial(26);

    rem1 (27) := rem1(27) xor polynomial(27);

    rem1 (28) := rem1(28) xor polynomial(28);

    rem1 (29) := rem1(29) xor polynomial(29);

    rem1 (30) := rem1(30) xor polynomial(30);

    rem1 (31) := rem1(31) xor polynomial(31);

    rem1 (32) := rem1(32) xor polynomial(32);

    end if;

    if (rem1 > polynomial) then

    fcs(31 downto 0) <= rem1(31 downto 0);

    g:=1;

    end if;

    end if;

    end if;

    end if;

    end process;

    end Behavioral;