bit by bit Data transfer

Without considering the question, if it's a meaningful application, I corrected your code by keeping the original structure as far as possible:

process(clk)
  variable mux_sel:std_logic_vector(2 downto 0):="000";
  variable i: integer range 0 to 63;
begin
  if (clk' event and clk='1') then
    if (rst_n='0')then
      tx_line<='0';
      mux_sel:="000";
      i:=0;
    end if;
  case mux_sel is
    when "000" =>
      tx_line<=fch(i);
      i:=i+1;
      if i > fch'high then
        mux_sel:=mux_sel+1;
        i:=0;
      end if;
-- continue respectively
  end case;

See the full design as attachment.

I understand, that a frame sync character is used, so the data could be possibly received without additional synchronisation. Regarding Stefaan's question, if the baud rate is actually intended to be full clock speed, I think it basically could be. I have a sensor interface using a 40 MHz UART frame from a MAX II device, but it uses a 320 MHz clock at the receiving FPGA. (160 MHz would be a minimum).

As Stefaan mentioned, the input has to be stable during transmission for consistent data. I also expect a lower resource requirement using a shift register, but in any case a lot of LEs is needed as multiplexer. If the timing constraints can be met with the existing construct, it must not necessarily changed.

Frank

P.S.: In case of a synchronous transmission, the frame could be received with the same clock.