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Altera_Forum
Honored Contributor
18 years agobit by bit Data transfer
Hello All.. I have problem in my code. I have created code for transmitting the data bit by bit. i.e.if my input (FCH)=1010101010101010=AAh then I'm Expecting 1010101010101010=AAh at tx_line o...
Altera_Forum
Honored Contributor
18 years agoMr BC
I still can not see why you should not use a shift register, and how you will use this in any practical design? If you tell me, maybe I can understand... As far as I can read VHDL, you just try to make a multiplexer driven by a counter. How are you going to synchronise the data again on the other end? Do you really want to run this serial line on the clock speed of the system? Is your clock is very slow? If you say you can resolve with a shift register, do it with a shift register then. It will be faster, less logic, simple implementation, ... Maybe you should latch your parallel data all at the same time before you send it out. Otherwise if some inputs change during the sending, the receiver sees inconsistent data. Stefaan