I am a newbie quartus user.. please help me thanks http://i54.tinypic.com/2zp2p3p.png This is my written code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity d4 is port (reset, sensor, load :in std_logic; p :in std_logic_vector (5 downto 0); led_on :out std_logic; q :out std_logic_vector (5 downto 0)); end d4; architecture flow of d4 is signal count_sig : unsigned (5 downto 0); signal load_sig : unsigned (5 downto 0); begin process (sensor, reset, load, p) begin if (reset = '1') then count_sig <= "000000"; elsif rising_edge (sensor) then if (count_sig = 32) then count_sig <= "000000"; else count_sig <= count_sig + 1; if (load = '0') then count_sig <= load_sig; else count_sig <= count_sig + 1; end if; end if; end if; end process; q <= std_logic_vector (count_sig); end flow; ------------------------------------------------------------------------ I did not add LED_ON in the code because i don't know the correct way to to put in the LED, always getting error when i try to put in LED code.. and i can't make P to activate Q when load is low. i don't know what i am talking about too. Please help me ! appreciate if u do so :confused:

LED_ON is just an output, you can assign it anywhere you want: LED_on <= '1'; or LED_on <= some_other_signal; or if something_happened then led_on <= '1'; else led_on <= '0'; end if; etc.

is LED_ON a predefined output? It's the second time i read about it.

--- Quote Start --- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity d4 is port (reset, sensor, load :in std_logic; p :in std_logic_vector (5 downto 0); led_on :out std_logic; q :out std_logic_vector (5 downto 0)); end d4; architecture flow of d4 is signal count_sig : unsigned (5 downto 0); signal load_sig : unsigned (5 downto 0); begin process (sensor, reset, load, p) begin if (reset = '1') then count_sig <= "000000"; elsif rising_edge (sensor) then if (count_sig = 32) then LED_ON <= '1'; count_sig <= "000000"; else LED_ON <= '0'; count_sig <= count_sig + 1; if (load = '0') then count_sig <= p; end if; end if; end if; end process; q <= std_logic_vector (count_sig); end flow;Try this. --- Quote End --- Error (10476): VHDL error at d4.vhdl(27): type of identifier "p" does not agree with its usage as UNSIGNED type thanks for assisting, it's not only the LED that i don't know about .. i feel that my code is not written properly and i can't find out the reason because i was not taught properly.. this one is way beyond my level

--- Quote Start --- Error (10476): VHDL error at d4.vhdl(27): type of identifier "p" does not agree with its usage as UNSIGNED type --- Quote End --- Truely. You need a type cast when assigning std_logic_vector to unsigned. Why don't you simply correct it and proceed.

Altera_Forum

Honored Contributor

15 years ago

BCD counter vhdl code

I am a newbie quartus user.. please help me thanks

http://i54.tinypic.com/2zp2p3p.png

This is my written code:

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity d4 is

port (reset, sensor, load :in std_logic;

p :in std_logic_vector (5 downto 0);

led_on :out std_logic;

q :out std_logic_vector (5 downto 0));

end d4;

architecture flow of d4 is

signal count_sig : unsigned (5 downto 0);

signal load_sig : unsigned (5 downto 0);

begin

process (sensor, reset, load, p)

begin

if (reset = '1') then

count_sig <= "000000";

elsif rising_edge (sensor) then

if (count_sig = 32) then

count_sig <= "000000";

else

count_sig <= count_sig + 1;

if (load = '0') then

count_sig <= load_sig;

else

count_sig <= count_sig + 1;

end if;

end process;

q <= std_logic_vector (count_sig);

end flow;

------------------------------------------------------------------------

I did not add LED_ON in the code because i don't know the correct way to to put in the LED, always getting error when i try to put in LED code..

and i can't make P to activate Q when load is low.

i don't know what i am talking about too. Please help me ! appreciate if u do so

:confused:

16 Replies

Altera_Forum
Honored Contributor
15 years ago
The code seems right: But you have twice "count_sig <= count_sig + 1;" in the code. But i don't think thats gonna affect the process.

I should try to adjust the test bench. Make load low for longer than a half a clk period. Make it low for 2 clk periods. Load works on a rising edge and load = '0'.
Altera_Forum
Honored Contributor
15 years ago
I told the reason for load not working in my previous post. Read it again. Or follow the above suggestion, but the waveform would be slightly different from the reference.

Also the led output is coming one cycle too soon, and with wrong polarity compared to the reference waveform. I also told a suggestion for this point.

--- Quote Start ---
But you have twice "count_sig <= count_sig + 1;" in the code. But i don't think thats gonna affect the process.
--- Quote End ---

Right, only the last assignment in a process wins, this property is also utilized for the load case. But the double assignment should be removed for clarity.
Altera_Forum
Honored Contributor
15 years ago
FvM and woody allen thanks for ur great help ! i hv got it working like it's suppose to already! thanks !
Altera_Forum
Honored Contributor
15 years ago
oops a minor problem.

http://i53.tinypic.com/35d6ek8.png
how to i fix this ?

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity d4 is
port (reset, sensor, load :in std_logic;
p :in std_logic_vector (4 downto 0);
led_on :out std_logic;
q :out std_logic_vector (4 downto 0));
end d4;

architecture flow of d4 is
signal count_sig : unsigned (4 downto 0);
signal led_flag : std_logic;

begin
process (sensor, reset, load, p)
begin
if (reset = '1') then
count_sig <= "00000";
elsif rising_edge (sensor) then
if count_sig = 31 then
led_flag <= '1';
count_sig <= (others => '0');
else
led_flag <= '0';
count_sig <= count_sig + 1;
led_on <= not led_flag;
if (load = '0') then
count_sig <= unsigned(p);

end if;
end if;
end if;
end process;

q <= std_logic_vector (count_sig);
end flow;

Altera_Forum

Honored Contributor

15 years ago

if (reset = '1') then
  count_sig <= "00000";
  led <= '1';
  led_flag <= '0';
elsif rising_edge (sensor) then

Altera_Forum
Honored Contributor
15 years ago
ok thanks...

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BCD counter vhdl code

16 Replies

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