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Altera_Forum
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15 years ago

BCD counter vhdl code

I am a newbie quartus user.. please help me thanks http://i54.tinypic.com/2zp2p3p.png This is my written code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; e...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

The code seems right: But you have twice "count_sig <= count_sig + 1;" in the code. But i don't think thats gonna affect the process.

I should try to adjust the test bench. Make load low for longer than a half a clk period. Make it low for 2 clk periods. Load works on a rising edge and load = '0'.