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Honored Contributor
Honored ContributorBCD counter vhdl code
I am a newbie quartus user.. please help me thanks http://i54.tinypic.com/2zp2p3p.png This is my written code: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; e...
Altera_ForumHonored Contributor
Honored Contributoroops a minor problem.
http://i53.tinypic.com/35d6ek8.png how to i fix this ?library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity d4 is
port (reset, sensor, load :in std_logic;
p :in std_logic_vector (4 downto 0);
led_on :out std_logic;
q :out std_logic_vector (4 downto 0));
end d4;
architecture flow of d4 is
signal count_sig : unsigned (4 downto 0);
signal led_flag : std_logic;
begin
process (sensor, reset, load, p)
begin
if (reset = '1') then
count_sig <= "00000";
elsif rising_edge (sensor) then
if count_sig = 31 then
led_flag <= '1';
count_sig <= (others => '0');
else
led_flag <= '0';
count_sig <= count_sig + 1;
led_on <= not led_flag;
if (load = '0') then
count_sig <= unsigned(p);
end if;
end if;
end if;
end process;
q <= std_logic_vector (count_sig);
end flow;
