Altera_Forum
Honored Contributor
12 years agoBasic Function Unit Design (ALU + shifter)
Hi,
I need to design the function unit attached in quartus. I decided to use Block Diagram/Schematic file then export as vhdl. Is there anything critical you think I should tweak before i start testing. Everything compiled without errors although I have warnings of; -No superset bus at connection -Pin ".. " is missing source -Primitive "XOR" of instance "inst1" not used -Warning(13410): Pin "F0" is stuck at GND Are these warnings fatal when exporting to VHDL code? thanks